IBM has unveiled a new chip design that could enable manufacturers to fit 100 billion transistors on a fingernail-sized silicon chip. The firm claims its new technology is the equivalent of around 0.7 nanometres and may make it the world's first known chip tech below 1nm.

However, Jay Gambetta, IBM Research director, describes the NanoStack as a 'landmark moment.' He says, 'We're not just making smaller transistors; we're reinventing how chips are built to deliver dramatically more power and energy efficiency.'

The new technology builds on previous innovations where IBM claimed its 2nm chip tech produced similar leaps in performance and energy efficiency. The more transistors that can be packed onto a chip, the more powerful it becomes, enhancing devices from smartphones to data centres.

Professor Alan Woodward at Surrey University compares IBM's NanoStack to constructing a 100-storey skyscraper instead of city houses. He adds that while Samsung and Intel are closer to 30-50 storeys with their own 3D chip work, IBM’s proposals could be the most ambitious.

The challenges for 3D chip designers include managing heat generated by transistors working in close proximity. However, if successful, this innovation could bring significant improvements in computing power and efficiency.